1. Field of the Invention
The present invention relates to a direct memory access (DMA) transfer control circuit used for an information processing system.
2. Description of Related Art
FIG. 9 is a block diagram showing a conventional direct memory access transfer control circuit (DMAC). In FIG. 9, 1 indicates a conventional direct memory access (DMA) transfer control circuit. 101, 102, - - - and 10N (N is an integer equal to or higher than 2) indicate a plurality of channel control units respectively. The number N denotes the number of channels. 2 indicates a DMA transfer control unit. In the channel control units 101 to 10N, a plurality of transfer request holding circuits 201, 202, - - - and 20N are disposed respectively. In the DMA transfer control unit 2, a channel transfer request arbitrating circuit 3 is disposed. A plurality of DMA transfer request signals DRQ1 to DRQN corresponding to the channels respectively are sent from modules (not shown) other than the conventional DMA transfer control circuit 1 to the transfer request holding circuits 201, 202, - - - and 20N of the conventional DMA transfer control circuit 1 respectively.
Next, an operation of the conventional DMA transfer control circuit 1 will be described below.
When a DMA transfer request signal DRQn (n is an arbitrary integral number ranging from 1 to N) is input to the channel control unit 10n of the conventional DMA transfer control circuit 1, the DMA transfer request signal DRQn is once held in the transfer request holding circuit 20n of the channel control unit 10n. Thereafter, the DMA transfer request signal DRQn held in the transfer request holding circuit 20n is fed to the DMA transfer control unit 2 as a channel transfer request.
Therefore, a plurality of DMA transfer request signals DRQ1 to DRQN sent from the other modules are received in the DMA transfer control unit 2 as a plurality of channel transfer requests respectively. In cases where a plurality of channel transfer requests are received in the DMA transfer control unit 2, the arbitration among the channel transfer requests is performed in the channel transfer request arbitrating circuit 3 of the DMA transfer control unit 2, and one channel transfer request is selected to determine the performance of a DMA transfer for the selected channel transfer request. In detail, priorities are set in advance for the channel transfer requests (or the channel transfer request signals). When a plurality of channel transfer requests are received in the DMA transfer control unit 2, a DMA transfer is assigned to one channel transfer request (hereinafter, called a top priority channel transfer request) having the top priority among those of the channel transfer requests. Thereafter, the DMA transfer is first performed for the top priority channel transfer request in a prescribed procedure. When the DMA transfer for the top priority channel transfer request is completed, a DMA transfer for the second priority channel transfer request is performed. Thereafter, the DMA transfers for the other channel transfer request signals are performed one after another in the order of lowering the priority of the channel transfer request.
Because the conventional DMA transfer control circuit has the above-described configuration, it is impossible to grasp how long the performance of the DMA transfer for each channel transfer request having the priority lower than that of the top priority channel transfer request is delayed. In other words, a transfer waiting time period of the DMA transfer performed in response to each remarked channel transfer request signal depends on the number of received channel transfer request signals having priorities higher than that of the remarked channel transfer request signal, and it is impossible to grasp the transfer waiting time period of the DMA transfer in the module corresponding to the remarked channel transfer request signal.
Therefore, in cases where the priority set in advance for the remarked channel transfer request signal is low, it takes a long time to perform the DMA transfer in response to the remarked channel transfer request signal. Therefore, a problem has arisen that it is difficult to set optimum priorities for a plurality of channel transfer request signals of the other modules. Also, in cases where the transfer waiting time period for the DMA transfer is prolonged, there is probability that a system error occurs. Because it is impossible to grasp the transfer waiting time period, another problem has arisen that it is impossible to prevent the occurrence of a system error in advance.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional DMA transfer control circuit, a DMA transfer control circuit in which a transfer waiting time period for a DMA transfer is shortened to efficiently perform the DMA transfer.
The object is achieved by the provision of a direct memory access transfer control circuit, comprising transfer control means for receiving N (N denotes an integral number equal to or higher than 2) DMA transfer requests composed of the first to N-th DMA transfer requests, assigning a plurality of DMA transfers to the N DMA transfer requests respectively according to priorities set in advance for the N DMA transfer requests and controlling the DMA transfers, and measuring means for measuring a time period from the reception of each DMA transfer request performed by the transfer control means to the assignment of the DMA transfer to the DMA transfer request performed by the transfer control means and outputting the time periods as a plurality of transfer waiting time periods of the N DMA transfer requests.
In the above configuration, in cases where a plurality of DMA transfers corresponding to a plurality of channels are performed, a transfer waiting time period from the reception of the DMA transfer request to the assignment of the DMA transfer can be grasped for each channel. Also, because the transfer waiting time period from the reception of the DMA transfer request to the assignment of the DMA transfer is grasped for each channel, the priority set for each DMA transfer request can be appropriately changed by comparing the transfer waiting time period of the DMA transfer request and a time before a system error occurs. Accordingly, the system error can be prevented.
It is preferred that the transfer waiting time period of each DMA transfer request is measured by the measuring means each time the DMA transfer request is received, and the transfer waiting time period longest among the time periods of one DMA transfer request is held by the measuring means as a maximum transfer waiting time period for each DMA transfer request.
Therefore, an operator can recognize the maximum transfer waiting time period for each DMA transfer request.
It is preferred that the transfer control means comprises a plurality of transfer request holding circuits for receiving the N DMA transfer requests respectively, holding the N DMA transfer requests respectively, and the measuring means comprises a plurality of counters for measuring a plurality of time periods from the holding of the DMA transfer requests in the transfer request holding circuits to the assignment of the DMA transfers to the DMA transfer requests in a count operation as the transfer waiting time periods of the N DMA transfer requests.
Therefore, the transfer waiting time period can be reliably measured for each DMA transfer request.
It is preferred that the direct memory access transfer control circuit further comprises a storing circuit for storing the transfer waiting time periods of the N DMA transfer requests, and reading means for selecting one of the transfer waiting time periods and reading out the selected transfer waiting time period.
Therefore, because the transfer waiting time period is stored in the storing means for each DMA transfer request, the order of the DMA transfers performed in response to the DMA transfer requests can be grasped. Also, in cases where a control method adopted in an information processing system and the priorities set in advance for the DMA transfer requests are reconsidered according to the transfer waiting time periods stored in the storing means, the DMA transfers for the DMA transfer requests can be efficiently performed.
It is preferred that the direct memory access transfer control circuit further comprises count control means for selecting one of the counters and feeding a count enabling signal to the selected counter so as to set the selected counter in a count enabling condition.
Therefore, because the measurement of the transfer waiting time period can be set for each counter, a degree of congestion of the DMA transfers can be minutely grasped.
It is preferred that the direct memory access transfer control circuit further comprises count control means for feeding a plurality of count enabling signals to all the counters respectively in response to an event signal input from an outside so as to set the counters in a count enabling condition.
Therefore, the measurement of the transfer waiting time period can be simultaneously set for all the counters.
It is preferred that the transfer control means comprises assigning means for assigning the DMA transfers to the N DMA transfer requests respectively according to the priorities set in advance for the N DMA transfer requests, receiving an emergency transfer request signal from a transfer request factor from which the n-th (n is an integral number ranging from 1 to N) DMA transfer request included among the N DMA transfer requests is sent out, and assigning the DMA transfer to the n-th DMA transfer request.
Therefore, there is no probability that no DMA transfer for the DMA transfer request is performed for a long time after the sending-out of the DMA transfer request, and the DMA transfer control circuit can prevent the occurrence of a system error.
It is preferred that the reception of the emergency transfer request signal is performed by the assigning means when a prescribed time period passes after the reception of the n-th DMA transfer request.
Therefore, the DMA transfer for the DMA transfer request can be reliably performed within a prescribed time period.
It is preferred that the direct memory access transfer control circuit further comprises comparing means for comparing the transfer waiting time periods output by the measuring means with a plurality of comparing values set in advance respectively, and outputting a comparison result agreement signal in cases where the n-th (n is an integral number ranging from 1 to N) transfer waiting time period included in the transfer waiting time periods agrees with the corresponding comparing value, and interrupting means for admitting the interruption of the n-th DMA transfer request included in the N DMA transfer requests in response to the comparison result agreement signal.
In the above configuration, when the n-th transfer waiting time period agrees with the corresponding comparing value, the interruption of the n-th DMA transfer request is admitted to assign the DMA transfer to the n-th DMA transfer request. Therefore, there is no probability that no DMA transfer is performed for the DMA transfer request set to a lower priority in advance.
The object is also achieved by the provision of a direct memory access transfer control circuit, in which N (N denotes an integral number equal to or higher than 2) DMA transfer requests composed of the first to N-th DMA transfer requests are received, a plurality of DMA transfers are assigned to the N DMA transfer requests respectively according to priorities set in advance for the N DMA transfer requests and the DMA transfers are controlled, comprising counting means for counting the number of DMA transfers for each DMA transfer request and obtaining a plurality of count values corresponding to the N DMA transfer requests, comparing means for comparing the count values obtained by the counting means with a plurality of comparing values set in advance respectively, and outputting a comparison result agreement signal in a case where the n-th (n is an integral number ranging from 1 to N) count value corresponding to the n-th DMA transfer request agrees with the corresponding comparing value, and priority changing means for changing the priorities set in advance for the N DMA transfer requests in response to the comparison result agreement signal output by the comparing means.
In the above configuration, in cases where the n-th count value agrees with the corresponding comparing value, the priorities set in advance for the DMA transfer requests are changed. Therefore, there is no probability that no DMA transfer is performed for the DMA transfer request signal set to a lower priority in advance.
It is preferred that the lowest priority is set for the n-th DMA transfer request corresponding to the n-th count value by the priority changing means in response to the comparison result agreement signal corresponding to the n-th count value.
Therefore, the comparing values are set in advance according to the priorities set in advance for the DMA transfer requests, and the lowest priority is set for the DMA transfer request in cases where the n-th count value agrees with the corresponding comparing value. Accordingly, the DMA transfers for the DMA transfer requests can be performed in a prescribed ratio among the number of DMA transfers for a plurality of first DMA transfer requests, the number of DMA transfers for a plurality of second DMA transfer requests, - - - and the number of DMA transfers for a plurality of N-th DMA transfer requests, and there is no probability that no DMA transfer is performed for the DMA transfer request set to a lower priority in advance.
It is preferred that the comparing values set in advance by the comparing means are determined according to the priorities set in advance for the N DMA transfer requests.
Therefore, the transfer waiting time period for each DMA transfer request can be shortened, and the DMA transfers for the DMA transfer requests can be efficiently performed.
It is preferred that the count value obtained by the counting means and corresponding to the n-th DMA transfer request is initialized by the priority changing means in response to the comparison result agreement signal.
Therefore, the priorities set for the N DMA transfer requests can be appropriately changed each time one count value agrees with the corresponding comparing value.